In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode more information.^[1]

When an ordinary modern computer is turned on, it starts by doing a power-on self-test (POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what memory timings to use to access the memory.

Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely override the SPD data (see overclocking).

Stored information

For a memory module to support SPD, the JEDEC standards require that certain parameters be in the lower 128 bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. Devices utilizing the memory automatically determine key parameters of the module by reading this information. For example, the SPD data on an SDRAM module might provide information about the CAS latency so the system can set this correctly without user intervention.

The SPD EEPROM firmware is accessed using SMBus, a variant of the I²C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

SPD EEPROMs also respond to I²C addresses 0x30–0x37 if they have not been write protected, and an extension (TSE series) uses addresses 0x18–0x1F to access an optional on-chip temperature sensor. All those values are seven-bit I²C addresses formed by a Device Type Identifier Code prefix (DTIC) with SA0-2: to read (1100) from slot 3, one uses 110 0011 = 0x33. With a final R/W bit it forms the 8-bit Device Select Code.^[2] Note that the semantics of slot-id is different for write-protection operations: for them they can be not passed by the SA pins at all.^[3]

Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

SDR SDRAM

The first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC100 memory specification introduced in 1998.^[4][5][6] Most values specified are in binary-coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".

The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.

SPD contents for SDR SDRAM^[7]

Byte		Bit								Notes
(dec.)	(hex.)	7	6	5	4	3	2	1	0
0	0x00	Number of bytes present								Typically 128
1	0x01	log2(size of SPD EEPROM)								Typically 8 (256 bytes)
2	0x02	Basic memory type (4: SPD SDRAM)
3	0x03	Bank 2 row address bits (0–15)				Bank 1 row address bits (1–15)				Bank 2 is 0 if same as bank 1
4	0x04	Bank 2 column address bits (0–15)				Bank 1 column address bits (1–15)				Bank 2 is 0 if same as bank 1
5	0x05	Number of RAM banks on module (1–255)								Commonly 1 or 2
6	0x06	Module data width low byte								Commonly 64, or 72 for ECC DIMMs
7	0x07	Module data width high byte								0, unless width ≥ 256 bits
8	0x08	Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–4)								Decoded by table lookup
9	0x09	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at highest CAS latency
10	0x0a	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				SDRAM access time from clock (tAC)
11	0x0b	DIMM configuration type (0–2): non-ECC, parity, ECC								Table lookup
12	0x0c	Self	Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz							Refresh requirements
13	0x0d	Bank 2 2×	Bank 1 primary SDRAM width (1–127, usually 8)							Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
14	0x0e	Bank 2 2×	Bank 1 ECC SDRAM width (0–127)							Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
15	0x0f	Clock delay for random column reads								Typically 1
16	0x10	Page	—	—	—	8	4	2	1	Burst lengths supported (bitmap)
17	0x11	Banks per SDRAM device (1–255)								Typically 2 or 4
18	0x12	—	7	6	5	4	3	2	1	CAS latencies supported (bitmap)
19	0x13	—	6	5	4	3	2	1	0	CS latencies supported (bitmap)
20	0x14	—	6	5	4	3	2	1	0	WE latencies supported (bitmap)
21	0x15	—	Redundant	Diff. clock	Registered data	Buffered data	On-card PLL	Registered addr.	Buffered addr.	Memory module feature bitmap
22	0x16	—	—	Upper Vcc (supply voltage) tolerance	Lower Vcc (supply voltage) tolerance	Write/1 read burst	Precharge all	Auto-precharge	Early RAS precharge	Memory chip feature support bitmap
23	0x17	Nanoseconds (4–18)				Tenths of nanoseconds (0–9: 0.0–0.9)				Clock cycle time at medium CAS latency
24	0x18	Nanoseconds (4–18)				Tenths of nanoseconds (0–9: 0.0–0.9)				Data access time from clock (tAC)
25	0x19	Nanoseconds (1–63)						0.25 ns (0–3: 0.00–0.75)		Clock cycle time at short CAS latency.
26	0x1a	Nanoseconds (1–63)						0.25 ns (0–3: 0.00–0.75)		Data access time from clock (tAC)
27	0x1b	Nanoseconds (1–255)								Minimum row precharge time (tRP)
28	0x1c	Nanoseconds (1–255)								Minimum row active–row active delay (tRRD)
29	0x1d	Nanoseconds (1–255)								Minimum RAS to CAS delay (tRCD)
30	0x1e	Nanoseconds (1–255)								Minimum active to precharge time (tRAS)
31	0x1f	512 MiB	256 MiB	128 MiB	64 MiB	32 MiB	16 MiB	8 MiB	4 MiB	Module bank density (bitmap). Two bits set if different size banks.
32	0x20	Sign (1: −)	Nanoseconds (0–7)			Tenths of nanoseconds (0–9: 0.0–0.9)				Address/command setup time from clock
33	0x21	Sign (1: −)	Nanoseconds (0–7)			Tenths of nanoseconds (0–9: 0.0–0.9)				Address/command hold time after clock
34	0x22	Sign (1: −)	Nanoseconds (0–7)			Tenths of nanoseconds (0–9: 0.0–0.9)				Data input setup time from clock
35	0x23	Sign (1: −)	Nanoseconds (0–7)			Tenths of nanoseconds (0–9: 0.0–0.9)				Data input hold time after clock
36–61	0x24–0x3d	Reserved								For future standardization
62	0x3e	Major revision (0–9)				Minor revision (0–9)				SPD revision level; e.g., 1.2
63	0x3f	Checksum								Sum of bytes 0–62, not then negated
64–71	0x40–47	Manufacturer JEDEC id.								Stored little-endian, trailing zero-padded
72	0x48	Module manufacturing location								Vendor-specific code
73–90	0x49–0x5a	Module part number								ASCII, space-padded
91–92	0x5b–0x5c	Module revision code								Vendor-specific code
93	0x5d	Tens of years (0–9: 0–90)				Years (0–9)				Manufacturing date (YYWW)
94	0x5e	Tens of weeks (0–5: 0–50)				Weeks (0–9)
95–98	0x5f–0x62	Module serial number								Vendor-specific code
99–125	0x63–0x7f	Manufacturer-specific data								Could be enhanced performance profile
126	0x7e	0x66 [sic] for 66 MHz, 0x64 for 100 MHz								Intel frequency support
127	0x7f	CLK0	CLK1	CLK3	CLK3	90/100 °C	CL3	CL2	Concurrent AP	Intel feature bitmap

DDR SDRAM

The DDR DIMM SPD format is an extension of the SDR SDRAM format. Mostly, parameter ranges are rescaled to accommodate higher speeds.

Zdroj:https://en.wikipedia.org?pojem=Serial_presence_detect
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SPD contents for DDR SDRAM^[8]

Byte		Bit								Notes
(dec.)	(hex.)	7	6	5	4	3	2	1	0
0	0x00	Number of bytes written								Typically 128
1	0x01	log2(size of SPD EEPROM)								Typically 8 (256 bytes)
2	0x02	Basic memory type (7 = DDR SDRAM)
3	0x03	Bank 2 row address bits (0–15)				Bank 1 row address bits (1–15)				Bank 2 is 0 if same as bank 1.
4	0x04	Bank 2 column address bits (0–15)				Bank 1 column address bits (1–15)				Bank 2 is 0 if same as bank 1.
5	0x05	Number of RAM banks on module (1–255)								Commonly 1 or 2
6	0x06	Module data width low byte								Commonly 64, or 72 for ECC DIMMs
7	0x07	Module data width high byte								0, unless width ≥ 256 bits
8	0x08	Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–5)								Decoded by table lookup
9	0x09	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at highest CAS latency.
10	0x0a	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				SDRAM access time from clock (tAC)
11	0x0b	DIMM configuration type (0–2): non-ECC, parity, ECC								Table lookup
12	0x0c	Self	Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz							Refresh requirements
13	0x0d	Bank 2 2×	Bank 1 primary SDRAM width (1–127)							Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
14	0x0e	Bank 2 2×	Bank 1 ECC SDRAM width (0–127)							Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set.
15	0x0f	Clock delay for random column reads								Typically 1
16	0x10	Page	—	—	—	8	4	2	1	Burst lengths supported (bitmap)
17	0x11	Banks per SDRAM device (1–255)								Typically 4
18	0x12	—	4	3.5	3	2.5	2	1.5	1	CAS latencies supported (bitmap)
19	0x13	—	6	5	4	3	2	1	0	CS latencies supported (bitmap)
20	0x14	—	6	5	4	3	2	1	0	WE latencies supported (bitmap)
21	0x15	—	x	Diff clock	FET switch external enable	FET switch on-board enable	On-card PLL	Registered	Buffered	Memory module feature bitmap
22	0x16	Fast AP	Concurrent auto precharge	Upper Vcc (supply voltage) tolerance	Lower Vcc (supply voltage) tolerance	—	—	—	Includes weak driver	Memory chip feature bitmap
23	0x17	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at medium CAS latency.
24	0x18	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data access time from clock (tAC)
25	0x19