Changes were made on 05/25/2024 and 06.06.2024 to the data bus width section, re-checking is required.

Computer memory and Computer data storage types
General Memory cell Memory coherence Cache coherence Memory hierarchy Memory access pattern Memory map Secondary storage MOS memory floating-gate Continuous availability Areal density (computer storage) Block (data storage) Object storage Direct-attached storage Network-attached storage Storage area network Block-level storage Single-instance storage Data Structured data Unstructured data Big data Metadata Data compression Data corruption Data cleansing Data degradation Data integrity Data security Data validation Data validation and reconciliation Data recovery Storage Data cluster Directory Shared resource File sharing File system Clustered file system Distributed file system Distributed file system for cloud Distributed data store Distributed database Database Data bank Data storage Data store Data deduplication Data structure Data redundancy Replication (computing) Memory refresh Storage record Information repository Knowledge base Computer file Object file File deletion File copying Backup Core dump Hex dump Data communication Information transfer Temporary file Copy protection Digital rights management Volume (computing) Boot sector Master boot record Volume boot record Disk array Disk image Disk mirroring Disk aggregation Disk partitioning Memory segmentation Locality of reference Logical disk Storage virtualization Virtual memory Memory-mapped file Software entropy Software rot In-memory database In-memory processing Persistence (computer science) Persistent data structure RAID Non-RAID drive architectures Memory paging Bank switching Grid computing Cloud computing Cloud storage Fog computing Edge computing Dew computing Amdahl's law Moore's law Kryder's law
Volatile
RAM Hardware cache CPU cache Scratchpad memory DRAM eDRAM SDRAM SGRAM LPDDR QDRSRAM EDO DRAM XDR DRAM RDRAM DDR GDDR HBM SRAM 1T-SRAM ReRAM QRAM Content-addressable memory (CAM) Computational RAM VRAM Dual-ported RAM Video RAM (dual-ported DRAM)
Historical Williams–Kilburn tube (1946–1947) Delay-line memory (1947) Mellon optical memory (1951) Selectron tube (1952) Dekatron T-RAM (2009) Z-RAM (2002–2010)
Non-volatile
ROM Diode matrix MROM PROM EPROM EEPROM ROM cartridge Solid-state storage (SSS) Flash memory is used in: Solid-state drive (SSD) Solid-state hybrid drive (SSHD) USB flash drive IBM FlashSystem Flash Core Module Memory card Memory Stick CompactFlash PC Card MultiMediaCard SD card SIM card SmartMedia Universal Flash Storage SxS MicroP2 XQD card Programmable metallization cell
NVRAM Memistor Memristor PCM (3D XPoint) MRAM Electrochemical RAM (ECRAM) Nano-RAM CBRAM
Early-stage NVRAM FeRAM ReRAM FeFET memory
Analog recording Phonograph cylinder Phonograph record Quadruplex videotape Vision Electronic Recording Apparatus Magnetic recording Magnetic storage Magnetic tape Magnetic-tape data storage Tape drive Tape library Digital Data Storage (DDS) Videotape Videocassette Cassette tape Linear Tape-Open Betamax 8 mm video format DV MiniDV MicroMV U-matic VHS S-VHS VHS-C D-VHS Hard disk drive
Optical 3D optical data storage Optical disc LaserDisc Compact Disc Digital Audio (CDDA) CD CD Video CD-R CD-RW Video CD Super Video CD Mini CD Nintendo optical discs CD-ROM Hyper CD-ROM DVD DVD+R DVD-Video DVD card DVD-RAM MiniDVD HD DVD Blu-ray Ultra HD Blu-ray Holographic Versatile Disc WORM
In development CBRAM Racetrack memory NRAM Millipede memory ECRAM Patterned media Holographic data storage Electronic quantum holography 5D optical data storage DNA digital data storage Universal memory Time crystal Quantum memory UltraRAM
Historical Paper data storage (1725) Punched card (1725) Punched tape (1725) Plugboard Drum memory (1932) Magnetic-core memory (1949) Plated-wire memory (1957) Core rope memory (1960s) Thin-film memory (1962) Disk pack (1962) Twistor memory (~1968) Bubble memory (~1970) Floppy disk (1971)
v t e

Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known as Mobile DDR, and abbreviated as mDDR.

Modern LPDDR SDRAM is distinct from DDR SDRAM, with various differences that make the technology more appropriate for the mobile application.^[1] LPDDR technology standards are developed independently of DDR standards, with LPDDR4X and even LPDDR5 for example being implemented prior to DDR5 SDRAM and offering far higher data rates than DDR4 SDRAM.

Bus width

Properties of the different LPDDR generations

LPDDR	1	1E	2	2E	3	3E	4	4X	5	5X
Maximum data bit width					32		64	64	32	32
Memory array clock (MHz)	200	266	200	266	200	266	200	266	400	533
Prefetch size	2n		4n		8n		16n
Memory densities			64 Mbit – 8 Gbit		1–32 Gbit		4–32 Gbit		4–32 Gbit
I/O bus clock frequency (MHz)	200	266	400	0533	0800	1067	1600	2133	3200	4267
Data transfer rate, DDR (MT/s)[a]	400	533	800	1067	1600	2133	3200	4267	6400	8533
Supply voltages (volts)	1.8		1.2, 1.8		1.2, 1.8		1.1, 1.8	0.6, 1.1, 1.8	0.5, 1.05, 1.8	0.5, 1.05, 1.8
Command/address bus	19 bits, SDR		10 bits, DDR				6 bits, SDR		7 bits, DDR
Year	2006		2009		2012		2014	2017	2019	2021

"proposal to the Wikipedia community to check the table above, the data obtained from the actual Samsung and Micron catalog on 6.06.2024 from semiconductor.samsung.com and micron.com official sites listing LPDDR3, LPDDR5 and LPDDR5 with a 64 bit width data (table contains a maximum of 32 bit data tire for LPDDR3/5/5X, also parameter "Maximum density (bit)" changed on "Maximum data bit width") contained models with its speeds and density not exceeding the values ​​of the table above What makes the recommendation update table: Micron MT62F2F2F2F8ZA-020 WT: C - 128 Gbit density at 9600 MT/S lpddr5 Samsung K3LKDKD0CM-BGCP lpddr5 - 144 Gbit density 6400 MT/s Samsung K3Klele0DM-BGCU lpddr5x - 144 Gbit density 8533 MT/s Samsung K3QFAFA0CM-AGCF lpddr3 - 64 Gbit density at 1866 MT/s applying 64 bit width data, but the previous models in the catalog cannot be found, its were removed from sites. In the catalogs there are models for various LPDRs as 16 and 32 and 64 bit data width."

In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.^[2]

The "E" and "X" versions mark enhanced versions of the specifications. They formalize overclocking the memory array by usually 33%.

As with standard SDRAM, most generations double the internal fetch size and external transfer speed. (DDR4 and LPDDR5 being the exceptions.)

Generations

LPDDR(1)

The original low-power DDR (sometimes retroactively called LPDDR1), released in 2006 is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption.

Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Samsung and Micron are two of the main providers of this technology, which is used in tablet and phone devices such as the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X.^[3]

LPDDR2

In 2009, the standards group JEDEC published JESD209-2, which defined a more dramatically revised low-power DDR interface.^[4][5] It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate either:

• LPDDR2-S2: 2n prefetch memory (like DDR1),
• LPDDR2-S4: 4n prefetch memory (like DDR2), or
• LPDDR2-N: Non-volatile (NAND flash) memory.

Low-power states are similar to basic LPDDR, with some additional partial array refresh options.

Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).

Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus. The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:

LPDDR2/LPDDR3 command encoding^[4]

Operation		↗ Rising clock ↗										↘ Falling clock ↘
		CA0 (RAS)	CA1 (CAS)	CA2 (WE)	CA3	CA4	CA5	CA6	CA7	CA8	CA9	CA0 (RAS)	CA1 (CAS)	CA2 (WE)	CA3	CA4	CA5	CA6	CA7	CA8	CA9
No operation		H	H	H	—
Precharge all banks		H	H	L	H	H	—
Precharge one bank		H	H	L	H	L	—		BA0	BA1	BA2	—
Preactive (LPDDR2-N only)		H	H	L	H	A30	A31	A32	BA0	BA1	BA2	A20	A21	A22	A23	A24	A25	A26	A27	A28	A29
Burst terminate		H	H	L	L	—
Read (AP=auto-precharge)		H	L	H	reserved		C1	C2	BA0	BA1	BA2	AP	C3	C4	C5	C6	C7	C8	C9	C10	C11
Write (AP=auto-precharge)		H	L	L	reserved		C1	C2	BA0	BA1	BA2	AP	C3	C4	C5	C6	C7	C8	C9	C10	C11
Activate (R0–14=Row address)		L	H	R8	R9	R10	R11	R12	BA0	BA1	BA2	R0	R1	R2	R3	R4	R5	R6	R7	R13	R14
Activate (LPDDR2-N only)		L	H	A15	A16	A17	A18	A19	BA0	BA1	BA2	A5	A6	A7	A8	A9	A10	A11	A12	A13	A14
Refresh all banks (LPDDR2-Sx only)		L	L	H	H	—
Refresh one bank (round-robin addressing)		L	L	H	L	—
Mode register read (MA0–7=address)		L	L	L	H	MA0	MA1	MA2	MA3	MA4	MA5	MA6	MA7	—
Mode register write (OP0–7=data)		L	L	L	L	MA0	MA1	MA2	MA3	MA4	MA5	MA6	MA7	OP0	OP1	OP2	OP3	OP4	OP5	OP6	OP7

Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.

LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:

• If the chip is active, it freezes in place.
• If the command is a NOP (CS low or CA0–2 = HHH), the chip idles.
• If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.
• If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)

The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a serial presence detect EEPROM, enough information is included to eliminate the need for one.

S2 devices smaller than 4 Gbit, and S4 devices smaller than 1 Gbit have only four banks. They ignore the BA2 signal, and do not support per-bank refresh.

Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.

Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.

Zdroj:https://en.wikipedia.org?pojem=LPDDR
Text je dostupný za podmienok Creative Commons Attribution/Share-Alike License 3.0 Unported; prípadne za ďalších podmienok. Podrobnejšie informácie nájdete na stránke Podmienky použitia.

---