A | B | C | D | E | F | G | H | CH | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
| Computer memory and Computer data storage types |
|---|
| Volatile |
| Non-volatile |
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
DRAM integrated circuits (ICs) produced from the early 1970s to early 1990s used an asynchronous interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a synchronous interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite-state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called banks, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.
Pipelining means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
History
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.[1][2]
The first commercial SDRAM was the Samsung KM48SL2000 memory chip, which had a capacity of 16 Mbit.[3] It was manufactured by Samsung Electronics using a CMOS (complementary metal–oxide–semiconductor) fabrication process in 1992,[4] and mass-produced in 1993.[3] By 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater performance.
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.
Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM.
Double data rate SDRAM, known as DDR SDRAM, was first demonstrated by Samsung in 1997.[5] Samsung released the first commercial DDR SDRAM chip (64 Mbit[6]) in June 1998,[7][8][9] followed soon after by Hyundai Electronics (now SK Hynix) the same year.[10]
SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.
Today, the world's largest manufacturers of SDRAM include: Samsung Electronics, SK Hynix, Micron Technology, and Nanya Technology.
Timing
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz = Hz) to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).
Control signals
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly active low, which are sampled on the rising edge of the clock:
- CKE clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
- CS chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
- DQM data mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
Command signals
- RAS, row address strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with CAS and WE, this selects one of eight commands.
- CAS, column address strobe. This is also not a strobe, rather a command bit. Along with RAS and WE, this selects one of eight commands.
- WE, write enable. Along with RAS and CAS, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.
Bank selection (BAn)
SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.
Addressing (A10/An)
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
Commands
The SDR SDRAM commands are defined as follows:
| CS | RAS | CAS | WE | BAn | A10 | An | Command |
|---|---|---|---|---|---|---|---|
| H | x | x | x | x | x | x | Command inhibit (no operation) |
| L | H | H | H | x | x | x | No operation |
| L | H | H | L | x | x | x | Burst terminate: stop a burst read or burst write in progress |
| L | H | L | H | bank | L | column | Read: read a burst of data from the currently active row |
| L | H | L | H | bank | H | column | Read with auto precharge: as above, and precharge (close row) when done |
| L | H | L | L | bank | L | column | Write: write a burst of data to the currently active row |
| L | Zdroj:https://en.wikipedia.org?pojem=Synchronous_dynamic_random-access_memory