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| Computer memory and Computer data storage types |
|---|
| Volatile |
| Non-volatile |
Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known as Mobile DDR, and abbreviated as mDDR.
Modern LPDDR SDRAM is distinct from DDR SDRAM, with various differences that make the technology more appropriate for the mobile application.[1] LPDDR technology standards are developed independently of DDR standards, with LPDDR4X and even LPDDR5 for example being implemented prior to DDR5 SDRAM and offering far higher data rates than DDR4 SDRAM.
Bus width
| LPDDR | 1 | 1E | 2 | 2E | 3 | 3E | 4 | 4X | 5 | 5X |
|---|---|---|---|---|---|---|---|---|---|---|
| Maximum data bit width | 32 | 64 | 64 | 32 | 32 | |||||
| Memory array clock (MHz) | 200 | 266 | 200 | 266 | 200 | 266 | 200 | 266 | 400 | 533 |
| Prefetch size | 2n | 4n | 8n | 16n | ||||||
| Memory densities | 64 Mbit – 8 Gbit | 1–32 Gbit | 4–32 Gbit | 4–32 Gbit | ||||||
| I/O bus clock frequency (MHz) | 200 | 266 | 400 | 533 | 800 | 1067 | 1600 | 2133 | 3200 | 4267 |
| Data transfer rate, DDR (MT/s)[a] | 400 | 533 | 800 | 1067 | 1600 | 2133 | 3200 | 4267 | 6400 | 8533 |
| Supply voltages (volts) | 1.8 | 1.2, 1.8 | 1.2, 1.8 | 1.1, 1.8 | 0.6, 1.1, 1.8 | 0.5, 1.05, 1.8 | 0.5, 1.05, 1.8 | |||
| Command/address bus | 19 bits, SDR | 10 bits, DDR | 6 bits, SDR | 7 bits, DDR | ||||||
| Year | 2006 | 2009 | 2012 | 2014 | 2017 | 2019 | 2021 | |||
In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.[2]
The "E" and "X" versions mark enhanced versions of the specifications. They formalize overclocking the memory array by usually 33%.
As with standard SDRAM, most generations double the internal fetch size and external transfer speed. (DDR4 and LPDDR5 being the exceptions.)
Generations
LPDDR(1)
The original low-power DDR (sometimes retroactively called LPDDR1), released in 2006 is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption.
Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Samsung and Micron are two of the main providers of this technology, which is used in tablet and phone devices such as the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X.[3]
LPDDR2
In 2009, the standards group JEDEC published JESD209-2, which defined a more dramatically revised low-power DDR interface.[4][5] It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate either:
- LPDDR2-S2: 2n prefetch memory (like DDR1),
- LPDDR2-S4: 4n prefetch memory (like DDR2), or
- LPDDR2-N: Non-volatile (NAND flash) memory.
Low-power states are similar to basic LPDDR, with some additional partial array refresh options.
Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).
Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus. The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:
| Operation | ↗ Rising clock ↗ | ↘ Falling clock ↘ | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CA0 (RAS) |
CA1 (CAS) |
CA2 (WE) |
CA3 |
CA4 |
CA5 |
CA6 |
CA7 |
CA8 |
CA9 |
CA0 (RAS) |
CA1 (CAS) |
CA2 (WE) |
CA3 |
CA4 |
CA5 |
CA6 |
CA7 |
CA8 |
CA9 | ||
| No operation | H | H | H | — | |||||||||||||||||
| Precharge all banks | H | H | L | H | H | — | |||||||||||||||
| Precharge one bank | H | H | L | H | L | — | BA0 | BA1 | BA2 | — | |||||||||||
| Preactive (LPDDR2-N only) | H | H | L | H | A30 | A31 | A32 | BA0 | BA1 | BA2 | A20 | A21 | A22 | A23 | A24 | A25 | A26 | A27 | A28 | A29 | |
| Burst terminate | H | H | L | L | — | ||||||||||||||||
| Read (AP=auto-precharge) | H | L | H | reserved | C1 | C2 | BA0 | BA1 | BA2 | AP | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | C11 | ||
| Write (AP=auto-precharge) | H | L | L | reserved | C1 | C2 | BA0 | BA1 | BA2 | AP | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | C11 | ||
| Activate (R0–14=Row address) | L | H | R8 | R9 | R10 | R11 | R12 | BA0 | BA1 | BA2 | R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | R13 | R14 | |
| Activate (LPDDR2-N only) | L | H | A15 | A16 | A17 | A18 | A19 | BA0 | BA1 | BA2 | A5 | A6 | A7 | A8 | A9 | A10 | A11 | A12 | A13 | A14 | |
| Refresh all banks (LPDDR2-Sx only) | L | L | H | H | — | ||||||||||||||||
| Refresh one bank (round-robin addressing) | L | L | H | L | — | ||||||||||||||||
| Mode register read (MA0–7=address) | L | L | L | H | MA0 | MA1 | MA2 | MA3 | MA4 | MA5 | MA6 | MA7 | — | ||||||||
| Mode register write (OP0–7=data) | L | L | L | L | MA0 | MA1 | MA2 | Zdroj:https://en.wikipedia.org?pojem=LPDDR4||||||||||||||